When I run the Verilog demonstration testbench, multiple instances of the following message occur at the beginning of the simulation:
"# Timing Violation Error : RST on instance pl4_demo_testbench.pl4_wrapper0.pl4_src_top0.\pl4_src_clk0/TSClkFullRate.tsclk_dcm0 must be asserted for 3 CLKIN clock cycles."
This error message is saying the RST of the DCM must be asserted for at lease 3 CLKIN cycles which is the requirement for the DCM.
The SPI4.2 testbench does appropriately assert the DCM resets for at least 3 CLKIN cycles. However, this problem is caused due to slightly different issue. In the testbench, the DCM Reset is initially defined as "x",then it changes to "1". This initial transition is evaluated as a valid transition, and starts the DCM Reset lenght check from this transition, therefore causing the ERROR.
This problem has been corrected in the 6.2i sp2 Simprim Model to only start the check from the valid Reset transtion of "1" to "0".