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AR# 18957

6.1.1 System Generator for DSP - Why does the clock probe have a phase offset?

説明

General Description: 

The SysGen Clock Probe block has a forced phase offset that causes the clock to transition slightly before XFix data transitions. This offset was originally added to assist visual analysis. Its inclusion has caused problems with the fixed-step solver and also in applications that assume the rising edge coincides with data transitions.

ソリューション

This has been fixed in System Generator 6.1.1. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 18957
日付 05/16/2014
ステータス アーカイブ
種類 一般
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