UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1903

Foundation Simulator - Unknown outputs on XBLOX or VHDL designs

説明

Keywords: simulate, unknown, XBLOX, VHDL

Urgency: Standard

General Description:
During functional simulation, the outputs of an XBLOX component--or a VHDL macro
containing inferred XBLOX components--are unknown.

ソリューション

This can happen if XBLOX is not being run prior to simulation. The Project Manager may
not detect the need to run an XBLOX update. If this happens, the simulation netlist will
contain XBLOX components that are not simulatable.

To force an XBLOX update, delete the <design>.alb and <design>.asx files, and run the
functional simulation again.
AR# 1903
作成日 02/10/1997
最終更新日 04/04/2001
ステータス アーカイブ
タイプ 一般