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AR# 19099

PowerPC - PowerPC could hang when the following conditions occur and exceptions are enabled


<a> CASE A: </a> 

PowerPC could hang when the following three conditions occur simultaneously: 

1. Store operation to OCM. 

2. Interrupt occurs around this OCM store operation. 

3. Store is followed immediately by a Load operation.  


The above conditions can cause the store and load operations to get out of order and ultimately cause the PowerPC-based system to hang. 


<a> Case B: </a>  

In addition, following corner conditions can also cause the system to hang: 


store reg, DSOCM <- exception occurs here 

store reg, DSOCM 




The same problem occurs when an exception hits a store multiple operation that saves more than one register to the DSOCM or when a store multiple follows a load: 



store multiple 29, DSOCM <- exception occurs here 





load reg, DSOCM 

store multiple 31, DSOCM <- exception occurs here  


If an exception hits at a certain cycle within the indicated instruction, the following happens. In cases A and B-(1) above, the load or store following the first store will show up on the DPLB instead of the DSOCM. In cases B-(2) and B-(3), all or parts of the store multiple will show up on the DPLB instead of the DSOCM. All four cases result in data corruption and dependent on the mapping of the DSOCM and DPLB peripherals in a bus error on the DPLB. 


The problem occurs independent of PPC:OCM clock ratios.


Suggested Work-around for "CASE A": 


1. Insert a "isync" instruction immediately after any OCM Stores that are followed by a load instruction.  

2. It is also recommended that you issue a "sync" instruction after "isync" in step 1, for PowerPC to complete any outstanding store transactions. 


Code Example (before): 


stw r4,0(r3) 

lwz r9,4(r3) 


Code Example (after): 


stw r4,0(r3) 



lwz r9,4(r3) 


"Case A" can also be resolved by adding a "nop" instruction between the store and the following load or store. 


Suggested Work-around for "CASE B": 


Case B-(1) can be resolved by adding a "nop" instruction between the store and the following store. 


Cases B-(2) and B-(3) cannot be resolved by software. The solution is to instruct the compiler/assembler not to generate store multiple instructions (existing compiler switch). 


None of the four cases occurs if exceptions are disabled. 


NOTE: Store and Load multiples are not generated by GCC unless the user turns them on explicitly.

AR# 19099
日付 05/16/2014
ステータス アーカイブ
種類 一般