UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19156

LogiCORE SPI-4.2 (POS-PHY L4) - Known Issues with Vitesse Framer

説明

General Description 

When using Xilinx SPI4.2 device with Vitesse Framer, you might run into following issues. The Vitesse part that is known to have problem is VSC9118. There might be others. 

 

The following issues are known regarding Vitesse VSC9118 Framer: 

1. Does not receive periodic training patterns correctly, must be turned off at Source side (Xilixn FPGA) 

2. Does not receive source sync data/clock correctly, needs clock or data phase shift to occur at Source side.

ソリューション

To work around the above two issues: 

 

1. Turn off sending of periodic training by setting xilinx SPI4.2 Source Core Static configuration setting: 

DataMaxT[15:0] or AlphaData[7:0] to zero.  

These settings can be found in SPI4.2 Core Generation GUI. 

 

2. To work around the source synchronous issue, please contact Xilinx Technical Support and open a WebCase. Networking IP experts will be able to assist you with this. 

http://www.xilinx.com/support/clearexpress/websupport.htm

AR# 19156
日付 05/16/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加