Can the HT core's transmit clock be used to clock internal logic in the upstream device?
The transmit clock from the core is created by a DCM. When RESET# is asserted, the DCM will not be outputting a stable transmit clock. This is true both during the initial RESET# and during a warm reset due to a link frequency change.
Since the transmit clock from the core drives the receive clock of the upstream device, it is important that the upstream device does not depend on this receive clock to clock internal logic including resetting internal state machines. Using an asynchronous reset by RESET# in the upstream device can avoid the dependence of its receive clock during RESET# assertion.
See page 64 of the HyperTransport Design Guide for more information. This can be found in the docs directory in the HyperTransport LogiCORE download.