UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19309

v2.0 Aurora Reference Design - Signal declared multiple times in "AURORA_SAMPLE.v" file

説明

General Description: 

The "AURORA_SAMPLE.v" file that is generated by the COREGen has the "ufc_tx_ack_i" signal declared multiple times.

ソリューション

To fix the problem, go to line 237, and comment out: 

 

wire ufc_tx_ack_i; 

 

This bug will be fixed in the next update of the Aurora Core.

AR# 19309
日付 05/16/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加