How do I access the Resets (ONBOARD_RST, SYSTEM_RST, RST, SYNC_RST) on the XtremeDSP Development Kit through the C/C++ API?
The following explanation of the resets on the XtremeDSP Development Kit II refers to these documents and examples:
- NUE Ping Application Note, shipped with the XtremeDSP Development Kit
- XtremeDSP Development Kit II User Guide
- C/C++ FUSE API
- Spartan-to-Virtex Interface
The ONBOARD_RESETl is the RSTl in the example in the Ping Application Note; it resets the DCM. The DCM-locked signal then feeds the actual RSTl on the SV_IFACE. Basically, the ONBOARD_RESETl controls the SV_IFACE RSTl. On the output of the SV_IFACE, there are two resets: SYNC_RST and RST. RST is an inverted version of the RSTl. On the other hand, SYNC_RST is an internally generated synchronous reset that is delayed by about three clock cycles. Consequently, it appears that RST and SYNC_RST are not directly controllable by you, but are generated based on the input RSTl to the SV_IFACE.
You can toggle SYSTEM_RESETl to reset a portion of your design. By default, SYSTEM_RESETl is connected to both the Clock FPGA and to the user FPGA so if you use this reset, you can tolerate a reset to the Clock FPGA as well.