How fast do ChipScope cores run?
The performance of the cores depends not only on the target device and speedgrade as well as the design they have been inserted into, but also on the size and complexity of the cores selected. Small simple cores can run well over 200MHz, and large (especially wide), complex cores will run much slower. How do you speed them up?
Here are some of the techniques that can be used for designs that no longer meet requirements after ChipScope Pro cores have been added:
- Reduce the size of your trigger port. Start with a basic trigger type, with a width as narrow as possible. An 8-bit basic trigger will consume a fraction of the logic of a 36-bit extended trigger, and might consequently run faster.
- Use "trigger same as data". By selecting trigger same as data, you reduce the number of loads on the design from two to one.
- Avoid critical paths. Understand the critical paths within your design and avoid instrumenting them if at all possible.
- Watch what you instrument. Avoid instrumenting combinatorial logic, which might cause the new implementation to split into multiple slices. Instrument the flip-flops instead.
- Apply area constraints to ChipScope Pro cores. Bound the inner logic of a ChipScope Pro core and allow the outer flip-flops to float. A tighter fit might result in higher performance.
- Properly constrain your design. Run "trace -a" to report unconstrained nets within your design. Apply period constraints where possible and use a constrained system clock to drive any ChipScope Pro cores.
- Disable RPMs. Sometimes allowing the ChipScope Pro core logic to float, particularly the flops that make up the cores, enables you to better fit ChipScope Pro cores within any available logic.