AR# 1984: FPGA Configuration: Address Pins A18 - A21 are optional for XC4000EX only
AR# 1984
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FPGA Configuration: Address Pins A18 - A21 are optional for XC4000EX only
説明
Keywords: address, xc4000ex
Urgency: Standard
General Description: The Configuration Address Pins A18, A19, A20, A21 are all high at the beginning of a Master Parallel configuration.
ソリューション
1
Since these lines are optional, they will act like unconfigured IOs until the portion of the bitstream to activate them is received. This means that A18-A21 will float high at the beginning of configuration. For Master Parallel Up configuration they need to be low from the beginning. This can be accomplished with a pulldown.
The Address Pins A18-21 are only activated by a bitgen option -g addresslines:<value>. The value specifies the total number of address lines to be activated. By default this number is 18. If you wanted A18 - A21 to be activated the bitgen syntax would be:
bitgen -g addresslines:22
2
In order to set the option to activate the upper address lines from the Design Manager GUI, you will need to perform the following steps :
1. Create a project for your design.
2. From the Utilities pull-down menu select Template Manager.
3. Select the "xc4000" Family from the top pull down menu and then select the "Configuration Template" buttton from the Template Manager window.
4. Select the New button and specify a name for your personal configuration template.
5. Being sure your template name is selected in the "Template List" window and press the "Customize" button.
