The value for TICCK is missing in the Virtex-II Pro Data Sheet - DS083 (v4.0) June 30, 2004. What does this value represent? Why is this value missing?
In master mode configuration, the FPGA sends CCLKs to the PROM during configuration. TICCK represents the delay between INIT going High and the output of CCLK.
0.250 us min
4.000 us max