When I run timing simulation (post-PAR simulation with SDF), the Source Core SPI-4.2 interface signals TDat_P/N and TCtl_P/N become undefined for several clock cycles (~ 4 TDClk_P cycles) after Reset_n is deasserted. After a few more clock cycles, TDat and TCtl settle to the correct defined value. This problem occurs in both VHDL and Verilog simulations.
This issue is apparent only in timing simulation, and you can safely ignore this behavior as the signals stabilize to the correct value after several TDClk cycles.
This issue will be resolved in a future software release.