A back-annotated timing netlist fails to account for input buffer delays when that input connects to a Fast/Direct Input Register. This might result in invalid setup time violations.
This issue is corrected in 7.1i.
For ISE versions 6.3i and earlier :
Follow the instructions below to work around this issue:
1. Modify the SDF file to include the proper delays. Please contact Xilinx technical support for assistance with this.
2. Turn off Direct Input Register usage in the CPLD Fitter Implementation Options. The fitter will not make use of direct input registers.
For ISE versions 6.x:
---- First, select Edit -> Preferences -> Processes Tab -> Property Display Level: Advanced.
---- Then, right-click Implement Design -> Fitting Tab -> (Advanced Options) Use Fast Input for Input Registers: OFF.