AR# 20120

6.3 System Generator for DSP - Why do I receive an error message stating that Verilog is not supported, even when I have VHDL selected in the Xilinx System Generator Block?

説明

General Description: 

In 6.3 System Generator for DSP, why do I receive an error message stating that Verilog is not supported, even when I have VHDL selected in the Xilinx System Generator Block?

ソリューション

This is a known issue when a design contains a block that is not currently supported in Verilog. 

 

You can find more information on the Verilog limitations, and how to work around them here: 

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_7_Section_16.htm  

 

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20120
日付 05/16/2014
ステータス アーカイブ
種類 一般