UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20205

8.1 System Generator for DSP - Why do I see a mismatch between the System Generator simulation and the Verilog behavioral simulation when using the Distributed or BlockRAM FIFO?

説明

Why do I see a mismatch between the System Generator simulation and the Verilog behavioral simulation when using the Distributed or BlockRAM FIFO?

ソリューション

It is currently known that the Verilog behavioral model for the Synchronous FIFO 5.0 Core does not match the System Generator for the DSP model. This problem occurs when you select Distributed or BlockRAM, but not when using the Embedded option. 

 

To work around this problem, you should perform a post translate simulation. 

 

This issue is fixed in System Generator for DSP 8.1.01, scheduled for release in April 2006.

AR# 20205
日付 05/16/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加