We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20239

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core - Incorrect array sizes in Verilog demonstration testbench (demo_tb.v)


General Description: 

There is a problem in the Verilog demonstration testbench (demo_tb.v) provided with the Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core. Specifically, the fixed array size defined in the frame_typ module in the "demo_tb.v" file is smaller than the four frames of stimulus defined in the testbench module. As a result, the last few bytes of the defined frame are missing in the simulated frames. 


However, since both the transmitter and receiver stimulus and monitor blocks use the same array, data in always equaled data out and the testbench passed. Close inspection of the data in the simulator wave window shows that the frames terminate part way through the FCS field of each frame. 


Even though this problem is relevant to all combinations, it results in an error only when the MGT CRC Enabled option is set to true.


There is a patch available to resolve this problem with the array sizes in the Verilog demonstration testbench (demo_tb.v). 


To obtain the fixed testbench, please install the patch that is available in the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core Release Notes and Known Issues Answer Record (Xilinx Answer 19880).

AR# 20239
日付 05/16/2014
ステータス アーカイブ
種類 一般