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AR# 20321

8.1i CPLD CPLDFit - Is there a feature to lock a previous placement in a CPLD such as the guide file for FPGA?


General Description: 

I would like to keep the same placement in my CPLD for some existing logic and add a new module. Is there a feature like the guide file for FPGA for CPLDs?


There is no automated way to do this. The solution is to create individual location constraints for all of the equations. The fitter report will give the equation names and locations, and you must create constraints for each equation. 


The following User Configuration File (UCF) constraint will instruct the design software to lock the equation 'my_output' to function block 1, macrocell 3: 


net my_output loc = FB1_3;

AR# 20321
日付 05/08/2014
ステータス アーカイブ
種類 一般