AR# 2037: M1/XSI v1.1.1a: Template runscripts in $XILINX/synopsys/examples are incorrect
AR# 2037
M1/XSI v1.1.1a: Template runscripts in $XILINX/synopsys/examples are incorrect
説明
keywords: M1,xsi,synopsys,runscript,instance
urgency: hot
general description: template runscripts in the $XILINX/synopsys/examples area are incorrectly write out the .sxnf or .sedif file before the ungroup -all -flatten procedure.
In general, this is alright, but if you are referencing register cell names withing the Synopsys environment, executing the write command before ungroup -all -flatten will result in instance name in the .ngd file which do not correspond to the names in the .ncf file.
For example, consider the following Synopsys timing constraint:
set_max_delay 100 -from "U2/U3" -to "U2/U4"
where U2/U3 and U2/U4 are FF instances names. If the .sxnf or .sedif file is produced before ungroup -all -flatten, the resulting .ngd file will have the FF's renamed to U2/U3/$1I13 and U2/U4/$1I13. Instances in the .ncf file will not correspond to the .ngd file. ngdbuild will be unable to create a .ngd file because it cannot find instances U2/U3 and U2/U4, because they now exist as U2/U3/$1I13 and U2/U4/$1I13.
To prevent this from happening, write out the .sxnf and .sedif file, *after* the ungroup -all -flatten command. This solution contains the corrected runscripts.
In general, this is only a problem with instance names of registers. If your timing constraints have referenced ports or signals/wires, this may not be an issue.
ソリューション
1
/* ==================================================*/ /* Sample Script for Synopsys to Xilinx Using */ /* FPGA Compiler */ /* */ /* Targets the Xilinx XC4028EX-3 and assumes a VHDL */ /* source file by way of an example. */ /* */ /* For general use with XC4000E/EX architectures. */ /* Not suitable for use with XC3000A/XC5200 */ /* architectures. */ /* ==================================================*/
/* ================================================= */ /* Set the name of the design's top-level module. */ /* (Makes the script more readable and portable.) */ /* Also set some useful variables to record the */ /* designer and company name. */ /* ================================================= */
TOP = <design_name> /* ========================== */ /* Note: Assumes design file- */ /* name and entity name are */ /* the same (minus extension) */ /* ========================== */
designer = "XSI Team" company = "Xilinx, Inc" part = "4028expg299-3"
/* ================================================= */ /* Analyze and Elaborate the design file and specify */ /* the design file format. */ /* ================================================= */
analyze -format vhdl TOP + ".vhd"
/* ============================ */ /* You must analyze lower-level */ /* hierarchy modules here */ /* ============================ */ elaborate TOP
/* ================================================= */ /* Set the current design to the top level. */ /* ================================================= */
current_design TOP
/* ================================================= */ /* Set the synthesis design constraints. */ /* ================================================= */
/* ================================================= */ /* Indicate those ports on the top-level module that */ /* should become chip-level I/O pads. Assign any I/O */ /* attributes or parameters and perform the I/O */ /* synthesis. */ /* ================================================= */
set_port_is_pad "*"
/* Some example I/O parameters */ set_pad_type -pullup <port_name> set_pad_type -no_clock all_inputs() set_pad_type -clock <clock_port_name> set_pad_type -exact BUFGS_F <hi_fanout_port_name> set_pad_type -slewrate HIGH all_outputs()
/* ============================= */ /* Note: Synopsys slew-control= */ /* HIGH is the same as Xilinx's */ /* slewrate=SLOW. Synopsys slew- */ /* control=LOW is same as Xilinx */ /* slewrate=FAST. */ /* ============================= */ insert_pads
/* ================================================= */ /* Synthesize and optimize the design */ /* ================================================= */
report_fpga > TOP + ".fpga" report_timing > TOP + ".timing"
/* ================================================= */ /* Write out the design to a DB file. (Post compile) */ /* ================================================= */
write -format db -hierarchy -output TOP + "_compiled.db"
/* ================================================= */ /* Replace CLBs and IOBs with gates. */ /* ================================================= */
replace_fpga
/* ================================================= */ /* Set the part type for the output netlist. */ /* ================================================= */
set_attribute TOP "part" -type string part
/* ================================================= */ /* Optional attribute to remove the FPGA Compiler's */ /* mapping structures from the design. This permits */ /* The Xilinx design implementation tools to map the */ /* design instead. */ /* ================================================= */
/* ================================================= */ /* Add any I/O constraints to the design. */ /* ================================================= */
/* ================================================= */ /* Write out the design to a DB. (Post replace_fpga) */ /* ================================================= */
write -format db -hierarchy -output TOP + ".db"
/* ================================================= */ /* Write-out the timing constraints that were */ /* applied earlier. (Note that any design hierarchy */ /* needs to be flattened before the constraints are */ /* written-out.) */ /* ================================================= */
ungroup -all -flatten write_script > TOP + ".dc"
/* ================================================= */ /* Save design in XNF format as <design>.sxnf */ /* ================================================= */
write -format xnf -hierarchy -output TOP + ".sxnf"
/* ================================================= */ /* Call the Synopsys-to-Xilinx constraints translator*/ /* utility DC2NCF to convert the Synopsys constraints*/ /* to a Xilinx NCF file. You may like to view */ /* dc2ncf.log to review the translation process. */ /* ================================================= */
/* ================================================= */ /* Now run the Xilinx design implementation tools. */ /* ================================================= */
2
/* ==================================================*/ /* Sample Script for Synopsys to Xilinx Using */ /* FPGA Compiler */ /* */ /* Targets the Xilinx XC5210-5 and assumes a VHDL */ /* source file by way of an example. */ /* */ /* For general use with XC3000A/L and XC5200 */ /* architectures. */ /* Not suitable for use with XC4000E/EX */ /* architectures. */ /* ==================================================*/
/* ================================================= */ /* Set the name of the design's top-level module. */ /* (Makes the script more readable and portable.) */ /* Also set some useful variables to record the */ /* designer and company name. */ /* ================================================= */
TOP = <design_name> /* ========================== */ /* Note: Assumes design file- */ /* name and entity name are */ /* the same (minus extension) */ /* ========================== */
designer = "XSI Team" company = "Xilinx, Inc" part = "5210pq160-5"
/* ================================================= */ /* Analyze and Elaborate the design file and specify */ /* the design file format. */ /* ================================================= */
analyze -format vhdl TOP + ".vhd"
/* ============================ */ /* You must analyze lower-level */ /* hierarchy modules here */ /* ============================ */ elaborate TOP
/* ================================================= */ /* Set the current design to the top level. */ /* ================================================= */
current_design TOP
/* ================================================= */ /* Set the synthesis design constraints. */ /* ================================================= */
/* ================================================= */ /* Indicate those ports on the top-level module that */ /* should become chip-level I/O pads. Assign any I/O */ /* attributes or parameters and perform the I/O */ /* synthesis. */ /* ================================================= */
set_port_is_pad "*"
/* Some example I/O parameters */ set_pad_type -pullup <port_name> set_pad_type -no_clock all_inputs() set_pad_type -clock <clock_port_name> set_pad_type -exact BUFG_F <hi_fanout_port_name> set_pad_type -slewrate HIGH all_outputs()
/* ============================= */ /* Note: Synopsys slew-control= */ /* HIGH is the same as Xilinx's */ /* slewrate=SLOW. Synopsys slew- */ /* control=LOW is same as Xilinx */ /* slewrate=FAST. */ /* ============================= */ insert_pads
/* ================================================= */ /* Synthesize and optimize the design */ /* ================================================= */
report_fpga > TOP + ".fpga" report_timing > TOP + ".timing"
/* ================================================= */ /* Set the part type for the output netlist. */ /* ================================================= */
set_attribute TOP "part" -type string part
/* ================================================= */ /* Optional attribute to remove the FPGA Compiler's */ /* mapping structures from the design. This permits */ /* The Xilinx design implementation tools to map the */ /* design instead. */ /* ================================================= */
/* ================================================= */ /* Add any I/O constraints to the design. */ /* ================================================= */
/* ================================================= */ /* Write out the design to a DB file. */ /* ================================================= */
write -format db -hierarchy -output TOP + ".db"
/* ================================================= */ /* Write-out the timing constraints that were */ /* applied earlier. (Note that any design hierarchy */ /* needs to be flattened before the constraints are */ /* written-out.) */ /* ================================================= */
ungroup -all -flatten write_script > TOP + ".dc"
/* ================================================= */ /* Save design in XNF format as <design>.sxnf */ /* ================================================= */
write -format xnf -hierarchy -output TOP + ".sxnf"
/* ================================================= */ /* Call the Synopsys-to-Xilinx constraints translator*/ /* utility DC2NCF to convert the Synopsys constraints*/ /* to a Xilinx NCF file. You may like to view */ /* dc2ncf.log to review the translation process. */ /* ================================================= */
/* ================================================= */ /* Now run the Xilinx design implementation tools. */ /* ================================================= */
3
/* ==================================================*/ /* Sample Script for Synopsys to Xilinx Using */ /* Design Compiler */ /* */ /* Targets the Xilinx XC4028EX-3 and assumes a VHDL */ /* source file by way of an example. */ /* */ /* For general use with all Xilinx architectures. */ /* ==================================================*/
/* ================================================= */ /* Set the name of the design's top-level module. */ /* (Makes the script more readable and portable.) */ /* Also set some useful variables to record the */ /* designer and company name. */ /* ================================================= */
TOP = <design_name> /* ========================== */ /* Note: Assumes design file- */ /* name and entity name are */ /* the same (minus extension) */ /* ========================== */
designer = "XSI Team" company = "Xilinx, Inc" part = "4028expg299-3"
/* ================================================= */ /* Analyze and Elaborate the design file and specify */ /* the design file format. */ /* ================================================= */
analyze -format vhdl TOP + ".vhd"
/* ============================ */ /* You must analyze lower-level */ /* hierarchy modules here */ /* ============================ */ elaborate TOP
/* ================================================= */ /* Set the current design to the top level. */ /* ================================================= */
current_design TOP
/* ================================================= */ /* Set the synthesis design constraints. */ /* ================================================= */
/* ================================================= */ /* Indicate those ports on the top-level module that */ /* should become chip-level I/O pads. Assign any I/O */ /* attributes or parameters and perform the I/O */ /* synthesis. */ /* ================================================= */
set_port_is_pad "*"
/* Some example I/O parameters */ set_pad_type -pullup <port_name> set_pad_type -no_clock all_inputs() set_pad_type -clock <clock_port_name> set_pad_type -exact BUFGS_F <hi_fanout_port_name> set_pad_type -slewrate HIGH all_outputs()
/* ============================= */ /* Note: Synopsys slew-control= */ /* HIGH is the same as Xilinx's */ /* slewrate=SLOW. Synopsys slew- */ /* control=LOW is same as Xilinx */ /* slewrate=FAST. */ /* ============================= */ insert_pads
/* ================================================= */ /* Synthesize and optimize the design */ /* ================================================= */
report_area > TOP + ".area" report_timing > TOP + ".timing"
/* ================================================= */ /* Set the part type for the output netlist. */ /* ================================================= */
set_attribute TOP "part" -type string part
/* ================================================= */ /* Add any I/O constraints to the design. */ /* ================================================= */
/* ================================================= */ /* Write out the design to a DB file. */ /* ================================================= */
write -format db -hierarchy -output TOP + ".db"
/* ================================================= */ /* Write-out the timing constraints that were */ /* applied earlier. (Note that any design hierarchy */ /* needs to be flattened before the constraints are */ /* written-out.) */ /* ================================================= */
ungroup -all -flatten write_script > TOP + ".dc"
/* ================================================= */ /* Save design in EDIF format as <design>.sedif */ /* ================================================= */
write -format edif -hierarchy -output TOP + ".sedif"
/* ================================================= */ /* Call the Synopsys-to-Xilinx constraint translator */ /* utility DC2NCF to convert the Synopsys constraints*/ /* to a Xilinx NCF file. You may like to view */ /* dc2ncf.log to review the translation process. */ /* ================================================= */
/* ================================================= */ /* Now run the Xilinx design implementation tools. */ /* ================================================= */
4
If you have already compiled the design, and already written out the .sxnf/.sedif files(If you run write before ungroup -all -flatten, multiple .sxnf/.sedif files will be created, then another possible workaround is to append the string $1I13 to all register instance names. For example, if a FF was named U2/U5/U7 and write was done before ungroup, then the edit the name in the .ncf file to U2/U5/U7/$1I13.
5
If you have already written out the .sxnf/.sedif files, another workaround is to re-read these files back into FPGA/Design Compiler, re-run ungroup -all -flatten, and the write out the .sxnf or .sedif file. This procedure will result in a single .sxnf or .sedif file being produced;This .sxnf or .sedif file will now correspond to the .ncf file produced earlier.