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AR# 2042

CONCEPT2XIL - Errors: "Unknown child port decl" and "Architecture not found"


Keywords: Concept2XIL, SIR2EDF

Urgency: Standard

General Description:
CONCEPT2XIL issues the message:

Expanding design hierarchy ...
Unknown child port decl: o
Occurrence andblox_0 -> top_lib.X_AND2.hdl: Error! Architecture not found in your design library.


Expanding design hierarchy ...
Occurrence AND1BINLD0 -> topcounter_lib.X_AND2.hdl: Error! Architecture not found in your design library


These two messages are generated if you are executing CONCEPT2XIL on a design that contains a LogiBLOX module or other non-schematic blocks for which you have generated a symbol using GENVIEW.

The "Error! Architecture not found in your design library" message is reported if the verilog.v file corresponding to the non-schematic block is missing the following parameter definition in the module declaration:

parameter cds_action = "ignore";

The solution is to add the cds_action="ignore" parameter to the offending non-schematic block verilog.v file.

The verilog.v file is usually located in the logic view (subdirectory) for the block. The parameter must be declared somewhere at the beginning of the Verilog module declaration for the block. Its function is to signal to the CONCEPT2XIL netlister that it should not try to find another level of hierarchy under the non-schematic block containing this parameter.

The "Unknown child port decl: o " is reported when the verilog.v file contains upper-case port names. Make sure to convert the module and port names to lower-case letters.
AR# 2042
日付 08/22/2003
ステータス アーカイブ
種類 ??????