UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20537

EDK 6.3 - Found in opb_ipif_v2_00_h and opb_ipif_v3_01_a: Modify size of FIFO to/from IP signals to be based on generics

説明

General Description: 

The current opb_ipif top-level entity port lists the following signals with a fixed length size of 32-bits: 

 

IP2RFIFO_Data & WFIFO2IP_Data 

 

The size of these signals should be based on the generic that specifies the width of the Rd and Wr FIFOs. When a 8-bit or 16-bit Rd/Wr FIFO is created in the opb_ipif, it does not match this top-level port signal size. 

 

The information for the size of these signals exists in the entity generic list. The two signals above can be edited as follows to create a working system: 

 

IP2RFIFO_Data : in std_logic_vector( 

0 to C_ARD_DWIDTH_ARRAY ( get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA)) - 1 )  

:= (others => '0'); 

 

WFIFO2IP_Data : out std_logic_vector( 

0 to C_ARD_DWIDTH_ARRAY ( get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)) - 1 ); 

 

 

NOTE: opb_ipif_v2_00_h is a deprecated core; thus, this modification will not be made for opb_ipif_v2_00_h.

ソリューション

This problem is fixed in the latest 6.3 EDK Service Pack, available at: 

http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.3 Service Pack 2.

AR# 20537
日付 05/16/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加