UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20620

6.3.p03 System Generator for DSP - Why do I see HDL simulation mismatches when the DSP48 PREG is not used?

説明

General Description: 

Why do I see HDL simulation mismatches when the DSP48 PREG is not used?

ソリューション

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20620
日付 05/16/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加