AR# 20624

6.3.p03 System Generator for DSP - Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

説明

General Description: 

Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

ソリューション

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20624
日付 05/19/2014
ステータス アーカイブ
種類 一般