AR# 20626

6.3.p03 System Generator for DSP - Why do I get a port mismatch error when using a Hardware in the Loop Co-Simulation block in a configurable subsystem?

説明

General Description: 

Why do I get a port mismatch error when using a Hardware in the Loop co-simulation block in a configurable subsystem? 

 

When a Hardware in the Loop co-simulation block is generated, the ports are sorted alphabetically. When a Subsystem is used with the configurable subsystem, the ports need to be arranged according to the port indexes. Because of this discrepancy, when a Hardware in the Loop block was used in a configurable subsystem, it could cause a port mismatch.

ソリューション

This has been fixed in System Generator 6.3.p03 for port counts less than 10, and now the ports for a Hardware in the Loop block are arranged according to index, rather than alphabetically. This should solve the problem of port mismatches when using the Hardware in the Loop block in a configurable subsystem. 

 

For designs with more than 10 ports, you should reduce the number of ports in the subsystem. This will be fixed in a future release of System Generator for DSP. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20626
日付 05/19/2014
ステータス アーカイブ
種類 一般