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AR# 20895

6.3 System Generator for DSP - Why does my output appear to be saturated when doing JTAG Hardware in the Loop Co-Simulation?

説明

General Description: 

Why does my output appear to be saturated when doing JTAG Hardware in the Loop Co-Simulation?

ソリューション

This usually occurs when the JTAG chain is not correctly defined. 

 

You must make sure to define the register lengths for all the devices in the chain. 

 

You can find more information about JTAG Hardware in the Loop Co-Simulation under the Using FPGA Hardware in the Loop of the System Generator for DSP Users Guide. 

 

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide.htm

AR# 20895
日付 05/19/2014
ステータス アーカイブ
種類 一般
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