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AR# 20962

8.2 System Generator for DSP - Why does System Generator for DSP hang when generating my large Verilog design?

説明

Why does System Generator for DSP hang when generating my large Verilog design?

ソリューション

This happens on a relatively small number of designs and will be addressed in System Generator for DSP 9.1. 

 

The process that is hanging is "xtclsh". 

 

You can kill the process by: 

 

1. Pressing <ctrl> <alt> and <delete> and selecting the Windows "Task Manager". 

2. Selecting the "Processes" tab. 

3. Click on "Image Name" to sort by process name. 

4. Right-click on the "xtclsh" process and select "End Process".

AR# 20962
日付 05/19/2014
ステータス アーカイブ
種類 一般
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