UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21003

7.1i CompXLib - SmartModels are not getting compiled for VHDL and Verilog

説明

Keywords: 6.3i, error, after, run, same, directory

Urgency: Standard

General Description:
When compiling VHDL and Verilog, both of the SmartModel wrappers are not getting compiled for the latter language. Why does this occur?

ソリューション

This is an issue with CompXLib . When both of the languages are used, CompXLib will only compile for Verilog and not compile for VHDL.

Always compile using the "-w" switch. This will overwrite the libraries, allowing you to work around the problem.

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21003
日付 11/18/2008
ステータス アーカイブ
種類 一般
このページをブックマークに追加