This Release Note is for the FIFO Generator v2.1 released in 7.1i IP Update 1 and available in 7.1i IP Update 2, and contains the following:
- New Features
- Bug Fixes
- Known Issues
NOTE: No updates or modifications were made to this core as a result of 7.1i IP Update 2; thus, the information included below still applies in IP Update 2.
For the installation instructions and design tool requirements for 7.1i IP Update 1, see (Xilinx Answer 21019).
For the installation instructions and design tool requirements for 7.1i IP Update 2, see (Xilinx Answer 21737).
New Features in v2.1
- Support added for Spartan-3E
- Support added for ISE 7.1i
- Support for First-Word Fall-Through (for block RAM and distributed RAM implementations)
- Support for Synchronous FIFO implementations utilizing the built-in Virtex-4 FIFO
- Improved cycle-accurate behavioral models for synchronous FIFO configuration
Bug Fixes in v2.1
CR 197104: GUI improvements
GUI re-designed for more intuitive usage
CR 196356, 197358: Programmable values out of range
Symptom: Programmable full and/or empty threshold values incorrectly set
CR 187328 : Handshaking Option dialog box is hidden
Symptom: The Handshaking Options dialog box might disappear behind the main FIFO Generator GUI on Solaris or Linux
CR 197000: GUI Allows invalid depths to be specified
Symptom: When selecting different aspect ratios, the GUI will allow an invalid depth to be selected
CR 197255: Verilog behavioral model - programmable empty incorrect
Symptom: The Verilog behavioral model of the synchronous FIFO is incorrect for PROG_EMPTY when the FIFO reaches the exact user-defined threshold
Known Issues in v2.1
- In addition to the data sheet, the User Guide is available for the FIFO Generator. To access the User Guide, generate the FIFO Generator v2.1 Core and search for "fifo_generator_ug175.pdf" in your COREGen project directory.
- In a FIFO16-based FIFO Generator implementation, when the output depth is larger than the selected Input Depth, it is possible for PROG_EMPTY and PROG_FULL to produce false-assert values if the Programmable Empty or Programmable Full thresholds are near the limits of their range.
See (Xilinx Answer 20278). (CR197535)
- During simulation, you might receive setup and hold time violations.
See (Xilinx Answer 20291). (CR197002)
- When using Independent clocks with Block Memory type, you might see an error during back-annotated simulation (gate-level and timing) at the reset.
See (Xilinx Answer 20271). (CR197268)
- When using Virtex-4 FIFO16 type, the behavioral model might not show true latency on the outputs. In this case, it is strongly recommended that you use Structural simulation model. Refer to User Guide chapter on "Simulating Your Design."