4) Check that all your paths are set properly by looking at the menu Options->System options. Only the ProjectPath setting should require modification by the user. Modify this path to point to c:\proj\myproj.
5) Select the module that you want to generate by clicking on the file icon in the Coregen GUI corresponding to the module.
6) For each module, a Data Sheet and a Description are available. Click on the green Icon labeled "Spec" to access the Data Sheet and click on Help->Help Topics to access the Module Description.
7) Fill out the fields as directed in the module Description and click on GENERATE.
*** NOTE *** Be careful not to name your module with a name that conflicts with a name of a Unified Library component. If you do, the Synthesizer will use the Unified Library XNF file instead of the one generated by CoreGen. Refer to the Libraries Guide for a listing of Unified Library components.
8) A VHDL instantiation template (module_name.VHI), a VHDL behavioral simulation netlist (module_name.vhd), and a Xilinx Netlist File (.XNF) will be created and copied into the Coregen working directory.
The VHDL instantiation template contains the component declaration as well as the Port Map declaration for the generated module. It can be Copied and Pasted into your Top Level VHDL file. A sample VHI file is listed below:
****** 8 Bit Adder VHDL Instantiation Template ad8.vhi *******
component ad8 port ( a: IN std_logic_VECTOR(7 downto 0); b: IN std_logic_VECTOR(7 downto 0); s: OUT std_logic_VECTOR(8 downto 0); c: IN std_logic; ce: IN std_logic; ci: IN std_logic; clr: IN std_logic); end component;
yourInstance : ad8 port map( a => a, b => b, s => s, c => c, ce => ce, ci => ci, clr => clr);
***********************************************
********** Top Level VHDL file: add8_top.vhd ******
Library IEEE; use IEEE.std_logic_1164.all;
entity add8_top is port ( INA,INB: in STD_LOGIC_VECTOR (7 downto 0); CLK, ce, ci, clr: in STD_LOGIC; QOUT: out STD_LOGIC_VECTOR (8 downto 0)); end add8_top;
architecture BEHAV of add8_top is
-- Instantiate the ad8.xnf file.
component ad8 port ( a: IN std_logic_VECTOR(7 downto 0); b: IN std_logic_VECTOR(7 downto 0); s: OUT std_logic_VECTOR(8 downto 0); c: IN std_logic; ce: IN std_logic; ci: IN std_logic; clr: IN std_logic); end component;
begin
u1 : ad8 port map ( a => ina, b => inb, s => qout, c => clk, ce => ce, ci => ci, clr => clr);
- When compiling, read in the design from bottom to top. - After compiling in Synopsys, do a remove_design on the ad8 design before writing out the .sxnf file. - In your run script this would appear as: