FPGA, Configuration, bypass, cclk, daisy chain, noise, ringing
GENERAL PROBLEM DESCRIPTION:
Device(s) in daisy chain seems to be in bypass mode and will
not configure properly.
The device(s) having problem can be any where in the chain and
can be one or multiple devices within the chain. You may
noticed that configuration data going in at DIN is coming right
out from DOUT one cclk cycle later, indicating that the device
is already full when it has not been configured yet.
Using logic analyzer or scope, check the signal on cclk near
the device having problem. A noise or ringing on cclk may be
the cause of this problem. In order to reduce the
noise/ringing, try adding 30-50 shunt capacitor on the cclk
Also, refer to Configuration Guideline Application note in the PFGA Databook for more debugging tips related to configuration problem.