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AR# 21271

7.1i Virtex-II PAR - クロック配置でエラーが発生する

説明

キーワード : Bank, clock, placer, BUFGMUX, バンク, クロック, 配置

重要度 : 標準

概要:
BUFGMUX のクロック領域の競合が原因で、クロック配置でエラーが発生します。
この問題は、IO バンクとクロック領域の相関関係が不正のために発生します。

ERROR:Place:44 - The global clocks dram_clk_2_bufg_inst (BUFGMUX6P) and
core_clk_2x_180_bufg_inst (BUFGMUX6S) are locked into a primary / secondary
site pair. It is impossible to route all of
the clock loads for both of these clocks using the global clock routing resource. Only one of
primary/secondary pair clocks have access to any one region via global (high
drive/low delay/low skew) routing resources. If these two clocks drive clock
inputs in the same clock region, the nets will not be routable using the
global clock routing resources.
Please correct this before continuing. The following component are causing
the problems. One group needs to be removed out of the area.

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_1_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_2_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_3_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions 3.2 (Checksum:1c9c37d) REAL time: 18 secs

ソリューション

この問題は、最新の 7.1i サービス パックで修正されています。サービス パックは、次のサイトからダウンロードできます。
http://www.xilinx.co.jp/xlnx/xil_sw_updates_home.jsp
これらの修正は、7.1i サービス パック 2 以降に含まれています。
AR# 21271
日付 10/20/2008
ステータス アーカイブ
種類 一般
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