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AR# 21346

LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Migrating from v7.1 to v7.2 (Migration Guide)

説明

General Description: 

This Answer Record describes how to migrate from v7.1 to v7.2 of the SPI-4.2 Core. It describes the signal changes made to the core. While every attempt was made to keep constraints and input and output signals as consistent as possible between versions, certain modifications are required to upgrade from v7.1 to v7.2. 

 

The following sections are included in this Answer Record: 

 

- Core Signal Changes 

- Wrapper File Changes 

- UCF File Changes

ソリューション

Core Signal Changes 

The following signal was removed from the v7.2 Sink Core : 

- RDClk180_GP(Output):Removed in v7.2, not used by the core. 

 

The following signals were removed from the v7.2 Source Core : 

- SysClk180_GP(Output): Removed in v7.2, not used by the core. 

- SysClk180_GBSL(Input): Removed in v7.2, not used by the Source Core in slave clocking mode. 

 

The following signal was added to the v7.2 Sink Core : 

- SnkClksRdy(Output): This signal indicates all Sink Core clocks are ready for use. If not needed, can be left unconnected. 

 

The following signal was added to the v7.2 Source Core :  

- SrcClksRdy(Output): This signal indicates all Source Core clocks are ready for use. If not needed, can be left unconnected. 

- DcmLost_TDClk (Output): This signal indicates whether the SysClk_P(N) input is lost. Only available when global clock distribution is used. If not needed, can be left unconnected. 

- DcmLost_TSClk (Output): This signal indicates whether the TSClk input is lost. Only available when global clock distribution is used. If not needed, can be left unconnected. 

 

For more information, see the user guide. 

 

 

Wrapper File Changes  

The v7.2 wrapper file replaces the v7.1 wrapper file. 

 

UCF File Changes  

The UCF file must be updated by replacing all SPI-4.2 constraints in the UCF file with SPI-4.2 constraints provided in the v7.2 release.

AR# 21346
日付 05/19/2014
ステータス アーカイブ
種類 一般
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