When I run the Verilog demo testbench with the FifoAFMode configuration to be "00", and when the core goes out of frame because it reaches the Almost Full threshold, the demo testbench does the following:
- It terminates the current packet immediately (not at a credit boundary). This causes the RDat Warning on protocol violation.
- Right after the last training data packet, the demo sends data without a control word . This is another protocol violation that causes RDat warnings and further data mismatches.
This is an issue with the demo testbench delivered with the SPI4.2 design example, and it is not an issue with the core. The core will still function with FifoAFMode set to "00". For this reason, when FifoAFMode = "00", expect to see protocol violations when FIFO reaches the Almost Full Threshold. This issue will be resolved in the next core release.