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AR# 21409

LogiCORE SPI-4.2 (POS-PHY L4) - PhaseAlignComplete never asserts, and SnkOof never de-asserts in simulation (Virtex-4 or Virtex-5)


When simulating the SPI-4.2 Dynamic Alignment Sink Core, the PhaseAlignComplete signal never asserts and SnkOof remains High, although the start-up sequence in (Xilinx Answer 16176) has been followed. This behavior can be seen in both post-NGDBuild and post-PAR (with SDF) simulations.


With Virtex-4 and Virtex-5 using Dynamic Phase Alignment (DPA), a significant number of cycles is required to complete the initial phase alignment at the startup. In a device, this takes only a second. However, this can take a few hours in a simulation, as you will need to run simulation long enough to see the PhaseAlignComplete assert and SnkOof de-assert. Once the core is in frame, there is no need to perform re-alignment. Therefore, it will not affect the overall bandwidth or the performance of the core. See SPI-4.2 User Guide, "Dynamic Alignment" section of "Sink Data Capture Implementation".  


In SPI-4.2 v7.4 and v8.1 Core  

The Dynamic Phase Alignment algorithm has changed and overall phase alignment time has shortened significantly. Please see respective User Guide ("Dynamic Phase Alignment" section) for approximate phase alignment completion time. To further reduce the phase alignment time, generate a simulation model with a smaller Alignment Test Interval. See SPI-4.2 User Guide, "Dynamic Alignment" section of "Sink Data Capture Implementation".  


In SPI-4.2 v7.3 and v7.2 Core 

The length of simulation time needed to complete the alignment for DPA will depend on the frequency of the RDClk. See SPI-4.2 User Guide, for Alignment Simulation Time for DPA. You can shorten the simulation time by doing one of the following: 


I. Use the shortened alignment simulation model (available for v7.2 and v7.3). See SPI-4.2 User Guide, "Shortened Alignment Simulation Model for Dynamic Phase Alignment" section for detail. 


II. Run the simulation in a batch mode rather than active GUI mode to reduce the simulation time. Refer to your simulator documentation on how to run simulation in batch mode and on how to properly save the simulation wave file for viewing at a later time.  


If you are performing Verilog simulation, Xilinx recommends that you generate a generic VCD file. To generate the VCD file, add the following code to your testbench (pl4_demo_testbench.v): 




$dumpvars(1, pl4_demo_testbench.pl4_wrapper0); 



You should have a "dcm_dv.vcd" file generated in your simulation directory, and be able to load it in the waveform viewer of your simulator. 


III. Use the static alignment simulation netlist. The steps needed to substitute the DPA simulation netlist with the Static simulation netlist are as follows: 


1. Open CORE Generator and load the project used to generate the original dynamic Phase Alignment Core. 

2. Select the original Dynamic Phase Alignment Core that you generated.  

3. Using the tool bar, choose to re-customize the core you selected (this will bring up the SPI-4.2 Core customization GUI).  

4. Change the "Component Name" option in the GUI to something other than what you have used to generate the DPA Core. 

5. Change the "Configuration" option in the GUI from "Dynamic Alignment" to "Static Alignment." 

6. Select the "Generate" button to generate the new core.  

7. Once the core is generated, go to the "<proj>/coregen/" directory; "<comp_name>_pl4_snk_top.v" will be generated.  

8. Copy this newly generated file to the directory of DPA simulation, and replace the original DPA simulation netlist. You should rename the DPA simulation netlist for backup in case you wish to simulate using DPA. 

9. Open the newly generated simulation file with a text editor and change the module (or entity name) defined at the top of the file to match the original module (or entity name) you have used for your Dynamic Phase Alignment Core.

AR# 21409
日付 05/19/2014
ステータス アーカイブ
種類 一般