library ieee, xc4000; use ieee.std_logic_1164.all; use xc4000.components.all; -- Include Synplify Xilinx Macro Libraries
entity LONG_LINE_EX1 is port (INBUSA, EN : in std_logic_vector(2 downto 0); SIGA : in std_logic_vector(1 downto 0); OUT_SIG : out std_logic); end LONG_LINE_EX1;
architecture XILINX of LONG_LINE_EX1 is
component PULLUP PORT (O : out std_logic); end component;
signal INT_SIG : std_logic;
begin
U0 : PULLUP port map (O => INT_SIG);
-- Infer tri-state buffers INT_SIG <= INBUSA(0) and SIGA(0) when (EN(0) = '1') else 'Z'; INT_SIG <= INBUSA(1) and SIGA(0) when (EN(1) = '1') else 'Z'; INT_SIG <= INBUSA(2) and SIGA(0) when (EN(2) = '1') else 'Z';