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AR# 216

SYNPLIFY: How to manage hierarchy using the syn_netlist_hierarchy and syn_hier attributes?

説明

Keywords: Synplify, hierarchy

Urgency: Standard

General Description: How to manage hierarchy with Synplify using the
syn_netlist_hierarchy and syn_hier attributes?

Synplify provides 2 attributes to manage hiearchy, syn_netlist_hierarchy
and syn_hier. The syn_netlist_hierarchy attribute when true maintains
hierarchy in the EDIF netlist. When 0, gives a flattened netlist (though
synthesis may still be maintaining hierarchy). The syn_hier is controls
hierarchy boundaries during synthesis. The syn_hier_netlist does not
affect synthesis, just the output from synthesis. While syn_hier affects
synthesis, and hence, maybe the output EDIF file.

When targeting Virtex designs, hierarchy can be preserved in the EDIF
netlist with the syn_netlist_hierarchy attribute. To specify the
syn_netlist_hierarchy attribute globally in the SDC file.

define_global_attribute syn_netlist_hierarchy 1

For non-Virtex designs, you should continue to accept the default of a
flattened hierarchy (syn_netlist_hierarchy = 0) of the EDIF netlist.
Setting this attribute to 0 will also cause the hierarchy in the Technology
View of HDL Analyst to be flattened.

"syn_hier" - Controls the amount of logic hierarchy flattening inside a
module or instance.

The syn_hier attribute is applied to instances, modules, or architectures.
It takes one of 5 values:

"soft" - The default option, and gives Synplify control over which
hierarchical boundaries to dissolve. Synplify chooses between "firm" and
"hard" depending upon which is optimum for your design unit. This attribute
affects only to the design unit it was specified in.

"firm" - Prevents a level of hierarchy from being dissolved, however, simple
boolean optimizations will still take place across hierarchical boundaries. This
attribute affects only to the design unit to which it was specified.

"hard" - Preserve the interface of the design unit with no exceptions. This
attribute affects only to the design unit to which it was specified.

"remove" - Dissolves a level of hierarchy in the design unit in which is was
specified. Hierarchy at lower levels are unaffected.

"flatten" - Flatten the hierarchy of all levels below, but not including, the one
in which it was specified. This value applies to optimization and mapping only.
By default, the hierarchy of your design is restored in the output netlist. This
restoration can be inhibited by setting a syn_netlist_hierarchy attribute to 0
(false) on the top-level module of your design.

The "flatten" value can optionally be used as the first value (followed by a
comma) in conjunction with the other values as shown below. If "flatten" is
used in conjunction with another value, Synplify will flatten as directed until
encountering another syn_hier attribute set at a lower level. The lower level
syn_hier attribute will then take precedence over the higher level one.

"flatten,soft" - The same as "flatten" by itself.

"flatten,firm" - Flatten all lower levels of the design but preserve the interface
of the design unit it was specified in and allow optimization of cell packing
across the boundary.

"flatten,remove" - Flatten all lower levels of the design including this one.

Notice that these options control the way Synplify handles a design during
optimization only. Regardless of which option is selected (remove, soft, hard,
firm, or hard), Synplify will rebuild the hierarchy before the final netlist is created,
ensuring that the netlist created by Synplify is efficient with regard to hierarchical
boundary optimizations, and structurally as close as possible to the source code.

ソリューション

1

Verilog
-------

module block_A (<port_interface>) /* synthesis syn_hier = "firm" */;

2

VHDL
----

VHDL:
attribute syn_hier: string;
attribute syn_hier of block_A : architecture is "firm";

3

SDC
---

define_attribute {U1} syn_hier {firm}

AR# 216
作成日 09/20/1995
最終更新日 11/20/2005
ステータス アーカイブ
タイプ 一般