We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21698

7.1i EDK SP2 - OPB_PCI core has errors in the MPD


General Description: 

OPB_PCI core has errors in the MPD. 


C_IPIF2PCI_FIFO_ABUS_WIDTH and C_PCI2IPIF_FIFO_ABUS_WIDTH of opb_pci has the following define, RANGE = (4:14). This is not correct. It should be some conditional range according to the core data sheet, 0 for NO FIFO, (4-12) for Virtex and (4-14) for Virtex-II. 


This error prevents running PlatGen when either one is set to 0, which is a valid value. 


The work around is to change the MPD file for this define to RANGE = (0:14).


This problem has been fixed in the latest 7.1i EDK Service Pack available at: 

The first service pack containing the fix is 7.1i EDK Service Pack 2.

AR# 21698
日付 05/19/2014
ステータス アーカイブ
種類 一般