Does the PCI Express Core support back-to-back transfers of TLP packets into the core on the TRN Tx inteface?
The core should support back-to-back transfers of TLP packets. This means that you can assert trn_teof_n on clock cycle n followed by trn_tsof_n on clock cycle n+1. However, in the v2.1.1 core and in previous cores, this does not work correctly because some packets are dropped during transmission. This issue is described in the release notes that accompany the download. This problem is currently being addressed and will be fixed in a future version of the core.
Currently, there must be at least one cycle between successive packets signaled by deasserting trn_tsrc_rdy_n. So the transfer sequence is assert trn_teof_n on clock cycle n to end the current packet, deassert trn_tsrc_rdy_n on clock cycle n+1 to insert a pause in the transfer, and then assert trn_tsrc_rdy_n and trn_tsof_n on clock cycle n+2 to start the new packet.
The one cycle of delay does not cause noticeable bandwidth reduction on the actual link due to the overhead inside the core as the packet moves through the core.