We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21863

7.1i Virtex-II MAP- "ERROR:PhysDesignRules:817 - The connectivity for pin ... of block ... is illegal. A child signal cannot exist for a pin of a leaf block."


General Description: 

A case has been seen where MAP failed with the error: 


ERROR:PhysDesignRules:817 - The connectivity for pin 

<registerClockHostReadToReshold(0)> of block 

<myWindow/myHookedUpLabVIEWThing/n_297624576> is illegal. A child signal 

cannot exist for a pin of a leaf block.  


This failure was caused by the existence of empty hierarchical blocks in the logical design.


This problem is scheduled to be fixed in version 8.2i. Meanwhile, the problem can be avoided by disabling KEEP HIERARCHY with the MAP switch "-ignore_keep_hierarchy" or by removing any "empty" hierarchical blocks from the design.

AR# 21863
日付 05/19/2014
ステータス アーカイブ
種類 一般