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AR# 2202

LEAPFROG: How to compile the Xilinx Alliance libraries for Cadence's Leapfrog?

説明

Keywords: VHDL, VITAL, Leapfrog, simulation, cv, ev

Urgency: Standard

General Description:
Xilinx does not directly test or support this simulator, however,
since it is a fully VITAL compliant simulator, as are the Xilinx VHDL
simulation libraries and simulation netlists, simulation of a Xilinx
design should be possible using this simulator.

ソリューション

Before a simulation may be performed on a Xilinx design, the VHDL
libraries must be compiled first. A CSH compile script is availible on
the Xilinx FTP site to assist in compiling the Xilinx libraries at:

http://www.xilinx.com/txpatches/pub/swhelp/cadence/leapfrog_libs.tar.Z

NGD2VHDL produces a VITAL compliant netlist of the implemented
design which can be compiled by the Leapfrog simulator.

For further details or information on compiling the VHDL libraries or
netlist for Leapfrog or any other questions concerning the simulator,
please consult the Cadence Openbook online documentation.

For further information on the Xilinx VHDL simulation libraries,
creating a Xilinx simulation netlist, or general information on Xilinx
VHDL simulation, please consult
(XAPP108: Chip-Level HDL Simulation Using the Xilinx Alliance Series)
at http://www.xilinx.com/xapp/xapp108.pdf
AR# 2202
作成日 08/31/2007
最終更新日 08/22/2003
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