Looking at the RC network on the DDR2 interface for the ML461 board, I see that some pins are marked as DNP, and some have a 5pF capacitor. Why is this?
The 5 PF termination is on only those signals that were supposedly reserved for the complementary data outputs to reduce SSO effect (but ultimately not implemented in the reference design), so this termination has no impact at all on the main line. Note that these are output only, nonfunctional signals.
For the same SSO reasons, a placeholder circuit was also added to provide a differential termination at FPGA, though the resistor is DNP (Do Not Populate) on the board BOM. DNP means that the differential termination is NOT provided; and it has a very minimal stub on the main line DQ signal between memory and FPGA.
Neither differential termination nor generation of negated output are implemented in the reference design because they did not seem to make any difference in SSO compensation.