We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

# AR# 22066

## 説明

キーワード : combinatorial, process, Verilog, 8.1i, 7.1i, 組み合わせ, プロセス

======================================================
module test_broken(a, y);
// Inputs and outputs
input [7:0] a;
output [7:0] y;
// Declare variables
reg [7:0] r;
reg [7:0] y;
// Declare iterator
integer i;
// Reverse input
always @(a) for (i = 0; i < 8; i = i + 1) r[i] = a[7-i];
always @(r) for (i = 0; i < 8; i = i + 1) y[i] = r[i] | i[0];
endmodule

=======================================================

## ソリューション

この問題を回避するには、次のように 2 つの異なる整数変数を使用します。

========================================================
module test_working(a, y);
// Inputs and outputs
input [7:0] a;
output [7:0] y;
// Declare variables
reg [7:0] r;
reg [7:0] y;
// Declare iterators
integer i, j;
// Reverse input
always @(a) for (i = 0; i < 8; i = i + 1) r[i] = a[7-i];
always @(r) for (j = 0; j < 8; j = j + 1) y[j] = r[j] | j[0];
endmodule
==========================================================

この問題は ISE 11.1 で修正される予定です。
AR# 22066

ステータス アクティブ

このページをブックマークに追加