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AR# 22141

7.1i CPLD TAEngine - "WARNING:Cpld:160 - The path from AAA to BBB cannot meet its TIMESPEC"


Why is the following warning produced? 


"WARNING:Cpld:160 - The path from signal X.Q to signal Y.D cannot meet its TIMESPEC. 

The delay of the path after optimization is 3.1ns. The TIMESPEC requires the path delay to  

be no greater than 2.5ns."


A "FROM: TO" constraint specifies the time allowed from one component to another component. 


If this time cannot be met, then a warning will be produced. In the CPLD timing report (or by using Timing Analyzer), you can examine the elements that make up the delay.  


The following is an excerpt from the CPLD timing report (design.tim). This shows the delay elements present in the path.  


From: counter<0> tCOI : 0.6ns (0.6ns) 

To: counter<2>.D tF + tLOGI1 + tSUI : 2.5ns (3.1ns) 


If you are unfamiliar with these abbreviations, reference the data sheet and the timing model Application Note for the appropriate device family: 


(Xilinx XAPP375): "Understanding the CoolRunner-II Timing Model." 

(Xilinx XAPP111): "Using the XC9500XL Timing Model." 


For further information on CPLD Timing see (Xilinx XAPP1047): "CPLD Timing" 


CPLDs, unlike FPGAs, have predictable routing delays, so the best way to minimize delays is to minimize the number of logic levels.

AR# 22141
日付 05/08/2014
ステータス アーカイブ
種類 一般