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AR# 22252

9.2i EDK - "ERROR:NgdBuild:455 - logical net 'net_gnd0' has multiple driver(s)"


When generating the hardware for an EDK design, the following INFO and ERROR messages occur during NGDBuild:

"INFO:NgdBuild:889 - Pad net 'net_gnd0' is not connected to an external port in

this design. A new port 'net_gnd0' has been added and is connected to this


ERROR:NgdBuild:455 - logical net 'net_gnd0' has multiple driver(s):

pin G on block XST_GND with type GND,

pin PAD on block plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/net_gnd0

with type PAD"

How do I resolve this issue?


There are likely IP core ports in the EDK system that instantiate input I/O buffers (such as IBUF) that are not connected to top-level ports. The EDK Platform Generator ties off this port to ground with the Gnd primitive and the net_gnd net. Then NGDBuild infers a port (pad) for this buffer, which creates an illegal connection between a pad, Gnd, and input buffer.

To resolve this error, check the MHS against the MPD files for each core to verify that all ports with instantiated I/O buffers (indicated with an IOB_STATE of BUF or REG) are connected to the top of the MHS.

Alternatively, the I/O buffers can be removed from the core.

AR# 22252
日付 02/21/2013
ステータス アクティブ
種類 一般