We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22608

8.1i XST - What is the recommended way to pass attributes in Verilog code?


Keywords: XST, IOSTANDARD, constraint, synthesis, attribute, 2001

Urgency: Standard

General Description:
In Verilog, there are two methods of passing the attributes; one is to use the meta comments and the other is to use the new Verilog 2001 method.

Which method is preferred?


Using the IOSTANDARD attribute as an example below:

Meta comments method:
//synthesis attribute IOSTANDARD of "rxd" is LVDCI_33;
//synthesis attribute IOSTANDARD of "data_ready" is LVDCI_33

Verilog-2001 method:
(* IOSTANDARD="LVDCI_33" *) input rxd ;
(* IOSTANDARD="LVDCI_33" *) output data_ready ;

When using XST, the preferred method is Verilog-2001. Xilinx is migrating away from meta comments for two reasons:
- Verilog-2001 method makes the code more portable.
- This is the direction the HDL industry is moving.

The XST User Guide will be updated in the future to use the Verilog-2001 methods. This is planned for ISE 9.1i.
AR# 22608
日付 01/08/2009
ステータス アーカイブ
種類 一般