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AR# 22665

LogiCORE Fibre Channel Arbitrated Loop v1.1 Core - Memory collisions occur during speed switch in demonstration testbench

説明

Occasionally, when simulating the Fibre Channel Arbitrated Loop v1.1 Core with the demonstration testbench, a memory collision error occurs in the example design FIFO when the testbench switches from the higher speed to the lower speed.

ソリューション

These memory collision errors can be safely ignored.

AR# 22665
日付 05/19/2014
ステータス アーカイブ
種類 一般
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