When simulating the core with NC-Sim, the write port output becomes undefined during read-write collision. This occurs when the write port operating mode of the Block Memory Generator Core is set to "Write First" or "No change". When a read-write collision occurs, the output of the write port becomes undefined.
To work around this issue, recompile UniSim and SimPrim libraries using the -RELAX option as follows:
1. Run compxlib -cfg.
2. Edit the "compxlib.cfg" file with -RELAX for the ncvhdl line.
3. Run compxlib.
This issue has been fixed with ISE8.1i Service Pack2.