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AR# 22709

8.2 System Generator for DSP - Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled?

説明

Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled?

ソリューション

You can work around this issue by using the DDS v5.0 block.

AR# 22709
日付 05/19/2014
ステータス アーカイブ
種類 一般
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