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AR# 2282

FPGA Express: Individual bits of a bus cannot be used as clock signals

説明


Urgency: Standard



General Description:

FPGA Express does not allow individual bits of a bus to be used as clock signals.

The following code will cause FPGA Express to crash:



<PRE>

library IEEE;

use IEEE.std_logic_1164.all;



entity busclk is

port (bigclk : in std_logic_vector(3 downto 0);

DIN : in std_logic_vector(3 downto 0);

RST, EN : in std_logic;

DOUT : out std_logic_vector(3 downto 0));

end busclk;



architecture busclk_arch of busclk is



begin



process( RST, bigclk(3), EN)begin

if( RST = '1' ) then

DOUT(3) <= '0';

elsif( bigclk(3)' event and bigclk(3) = '1' )then

if( EN = '1' )then

DOUT(3) <= DIN(3);

end if;

end if;

end process;

...



end busclk_arch;

</PRE>

ソリューション


The workaround is to assign the bus bit to an intermediate signal first, as shown:



<PRE>

library IEEE;

use IEEE.std_logic_1164.all;



entity busclk is

port (bigclk : in std_logic_vector(3 downto 0);

DIN : in std_logic_vector(3 downto 0);

RST, EN : in std_logic;

DOUT : out std_logic_vector(3 downto 0));

end busclk;



architecture busclk_arch of busclk is



signal intclk3: std_logic;



begin



intclk3 <= bigclk(3);



process( RST, intclk3, EN)begin

if( RST = '1' ) then

DOUT(3) <= '0';

elsif( intclk3' event and intclk3 = '1' )then

if( EN = '1' )then

DOUT(3) <= DIN(3);

end if;

end if;

end process;

...



end busclk_arch;

</PRE>
AR# 2282
作成日 08/31/2007
最終更新日 04/10/2012
ステータス アーカイブ
タイプ 一般