UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23591

LogiCORE Multiplier v8.0 - The SCLR does not reset the upper bits of a DSP48-based 35 x 18 multiplier. Why?

説明

The SCLR does not reset the upper bits of a DSP48-based 35 x 18 multiplier. Why?

ソリューション

This is a known bug in the reset of the Multiplier v8.0, and is fixed in Multiplier v9.0. 

 

The way to work around this issue is to infer registers with a reset at the output of the multiplier, using HDL.

AR# 23591
日付 05/20/2014
ステータス アーカイブ
種類 一般
このページをブックマークに追加