We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2371

Schematic - A schematic can be written despite error from reserved names used in design


If reserved names such as "input" or "output" are used for signals in a design, Cadence will report the error but still allow the netlist to be written. This netlist is likely to cause problems for other design tools.


Remove or change all signals causing error messages, regardless of whether the netlist is written.

AR# 2371
日付 05/08/2014
ステータス アーカイブ
タイプ 一般